1. Field of the Invention
The present invention relates to a cylindrical storage capacitor for a memory cell and a method for fabricating the same, and more particularly to a cylindrical storage capacitor for a memory cell in which a hemispherical grain silicon (HGS) is grown only at the inner and top surfaces of a polycrystalline silicon (hereinafter referred to as "polysilicon") layer for use in the cylindrical storage electrode, capable of increasing a capacitance of the storage capacitor and securing a margin for the prevention of the contact misalignment between the storage electrode and a buried contact, and a method for fabricating such storage capacitor.
2. Description of the Related Art
Generally, memory cells of semiconductor memory devices, for example, dynamic random access memory (DRAM), include a transistor and a storage capacitor. When memory cell area is reduced for high integration of DRAM, the transistor area and the storage capacitor area on a semiconductor substrate are also reduced. This results in reduction in capacitance of a typical storage capacitor having a two-dimensional structure.
As capacitance of a storage capacitor is reduced, the ratio of signal to noise is lowered, and the soft error occurrence rate due to a particle is increased. Therefore, sufficient capacitance for the storage capacitor is required even though a high integration of DRAM is achieved.
To obtain a sufficient capacitance, there have been endeavours of reducing thickness of dielectric film, developing a new dielectric film having a large dielectric constant, or extending an effective surface area of the storage capacitor. Studies on dielectric films have been developed a lot, and the storage capacitor having a three-dimensional structure has been suggested to improve cell capacitance. The storage capacitor can be roughly classified into a trench type and a stacked type.
In the trench type storage capacitor, a trench is formed on a semiconductor substrate and a dielectric film and a polysilicon layer for use as electrode are deposited in the trench, which may cause complexity in a manufacturing process. Moreover, an electric leakage or a punch through between trenches is likely to occur.
In the stacked type storage capacitor, a dielectric film and a polysilicon layer for use as electrode are deposited on a semiconductor substrate, which simplifies a manufacturing process while eliminating such electrical problems. Accordingly, the stacked type storage capacitor is gaining in popularity.
As the DRAM becomes highly integrated in a limited area, the storage capacitor area in the memory cell is also reduced. Therefore, it is not easy to obtain a target capacitance for the stacked type storage capacitor. To overcome such problem, a method of making a storage electrode made of a polysilicon layer higher as possible without bringing any damage to the storage electrode, has been proposed. In this method, the storage electrode has to be maintained at 10,000 .ANG. or higher when considering the current memory cell area. If the storage electrode is 10,000 .ANG. or lower, the target capacitance may not be obtained.
If the memory cell area is further reduced, the storage electrode has to be higher. The method of overcoming such problem was disclosed in "A new cylindrical capacitor using hemispherical grain silicon for 256 Mb DRAMs", by Watanabe in international electronic device & material (IEDM) 1992, pp. 259-262. In the paper, Watanabe applies a hemispherical grain silicon to the storage electrode of the storage capacitor, in which the hemispherical grain silicon is grown at the overall surface of a cylindrical storage electrode so as to extend an effective surface area of the storage electrode and thus obtain the target capacitance.
Since Watanabe, the method growing the hemispherical grain silicon at the surface of the storage electrode with maintaining the height of the storage capacitor at 10,000 .ANG. or more has been widely used. However, this method has some disadvantages in application to mass production. In other words, margin of critical dimension is insufficient during the application of a photolithography or a dry etching process. In addition, a micro bridge may occur due to formation of the hemispherical grain silicon, which may cause a twin bit failure.
To prevent micro bridges, the storage electrode area in the limited memory cell area should be reduced. Then, such the reduction in the storage electrode area may cause misalignment between the buried contact and the storage capacitor. Therefore, it is difficult not only to secure a sufficient margin for the prevention of such the misalignment when considering critical dimension of the present photolithographic process, but complexity in process for fabricating such the memory cell is indispensable.
To overcome such problem, various new methods for forming storage electrodes have been proposed. As one method of them, there is provided a method for forming a cylindrical storage electrode where a single hole is formed in the stacked storage electrode so as to extend the surface area of the storage electrode. However, a number of processes are added in this method, which makes the manufacturing process more complicated.
Recently, a damascene process is employed in the formation of the cylindrical storage electrode in order to increase a capacitance of the storage capacitor and obtain sufficient margin against a misalignment with the buried contact. Here, an oxide film has to be vertically dry-etched to a desired depth so as to form an opening part corresponding to the storage electrode pattern.
However, the dry etching method may cause a tail in the lower edge portions of the etched surface if it is not over-etched, which prevents obtaining fine vertical profile of the etched surface. Thereafter, the storage electrode is formed within the opening part and the oxide film is then removed. Subsequently, when a dielectric film and a polysilicon layer for a plate electrode are deposited in the order named on the surface of the storage electrode and an insulator film is deposited thereon, a void is caused in the region where the tail exists.
In addition, the polysilicon layer for formation of the storage electrode is deposited on the oxide film having the opening part and the polysilicon layer except for the opening part is then polished by a chemical and mechanical polishing process. Thereafter, the oxide is removed by a wet etch. At this time, the tail may not be completely removed when the oxide film is lift off by such the wet etch. Therefore, the oxide film has to be over-etched for a complete removal of the tail. The amount of wet-etched oxide film depends on the time spent in the wet etching. Therefore, it is very difficult not only to control such the wet etch time but process reproduction is lowered.
Micro bridge is likely to occur when the hemispherical grain silicon is grown at the surface of the polysilicon layer for the storage electrode so as to increase a capacitance. Thus, sufficient margin for prevention of the twin bit failure may not be obtained. For preventing such shortcoming, if the outer bottom surface area of the storage electrode is reduced, the capacitance is also reduced. In addition, an area which the storage electrode contacts with the buried contact is reduced. Then, the margin against the contact misalignment between the storage electrode and the buried contact may not be obtained.
From such various reasons, the conventional method for fabricating cylindrical storage capacitor cannot be applied to a mass production of the storage capacitors.